Responsibilities
• Develop test plans using established methodologies targeted on chip IP functions and features.
• Design and implement test circuits using FPGA fabric and embedded IP using Lattice’s proprietary design SW.
• Develop scripts to automate test generation and own Pre-Si verification of content to ensure Si readiness.
• Execute Post-Si pattern validation using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions.
• Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.)
• Take ownership of IP content development and drive any issues to resolution.
• Plan and execute test content delivery to meet or exceed schedules required for internal and external customers samples.
• Extract coverage metrics of test patterns using fault grading and review for coverage improvements.
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