Design Engineer Intern - Modeling

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Key Responsibilities

• Develop and validate IP behavioral models using Verilog/SystemVerilog/SystemC
• Perform functional testing, audits, and consistency checks against reference RTL and specifications
• Support generation and validation of HW deliverables for SW enablement, including timing, power, and signal-integrity models
• Assist in debugging model, integration, and SW-facing issues across the IP development lifecycle
• Develop automation and scripts to improve model generation, validation, and release processes
• Collaborate with cross-functional teams (IP, DV, Integration, and SW) to ensure model quality and usability