Accountabilities/Exposure:
- Own unit level design and IP integration.
- Own design quality check with exposure to various industry standard EDA tool and methodology.
- Design timing constraints definition and timing convergence.
- Design openbox test planning, assertion check coding and debug.
- Design code coverage analysis and closure.
- Scripting in flow automation on daily design execution tasks.
Qualification:
- Good understanding in ASIC/FPGA IP or SoC development cycle.
- Proficient in RTL design with Verilog or System Verilog and design constraints.
- Exposure in design quality checks methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.
- Programming skills (e.g.: Perl, Shell Scripting, TCL, Java, Python or C/C++) and familiar with Linux OS.
- Self-motivated, strong communication skills, promote innovation and teamwork.