Principal Architecture Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

The FPGA Architecture Team at Lattice Semiconductor is seeking a Principal FPGA Architect to build and lead a team of FPGA architecture evaluation experts focused on shaping the next generation of FPGA architectures and tools. This role sits at the intersection of RTL design, FPGA architecture, and design methodology, with a strong emphasis on hands-on FPGA implementation and analysis rather than abstract modeling alone.

The successful candidate will define and drive a methodology for implementing representative and forward-looking FPGA workloads on existing and future FPGA architectures, analyzing results, and providing actionable architectural feedback. The goal is to influence FPGA hardware features, microarchitecture, and EDA tools to deliver optimal power, performance, area, and usability for real customer designs.

This role includes technical leadership and team building, close collaboration with FPGA architects, RTL designers, EDA/tool teams, and silicon validation, and ownership of architectural insights from early exploration through silicon correlation.

Responsibilities:

• Build, mentor, and lead a team of FPGA architecture evaluation and analysis engineers.
• Define and execute a strategy for RTL-based FPGA architecture evaluation, using realistic workloads and design patterns.
• Implement, synthesize, place-and-route, and analyze complex FPGA designs across multiple architectures and process generations.
• Evaluate architectural tradeoffs involving:
  • Logic, routing, memory, DSP, and interconnect structures
  • Timing closure, routability, utilization, and power efficiency
  • Tool behavior, compile time, and QoR sensitivity
• Provide clear, data-driven feedback to FPGA architecture teams to guide:
  • Hardware feature definition and optimization
  • Microarchitectural changes
  • Tool and flow improvements
• Correlate architectural hypotheses with RTL results, post-P&R data, and silicon measurements where available.
• Drive design-space exploration using RTL and FPGA tools rather than purely abstract models.
• Partner with EDA, software, and silicon teams to ensure architectural intent translates into real-world results.
• Represent the evaluation team in architectural reviews and cross-functional forums.