Design Verification Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

As a Verification Eng., you will work with IP architect to understand IP features, create testbench architecture plan, work with IP designers to develop testplan, perform detailed testing of IP features and ensure coverage is met. You will need to ensure the IP is compatible with industry standard synthesis & simulator tools. You will also co-ordinate with IP designer on IP release mechanism for testing. You are also expected to develop scripts in Python and other script language to automate the soft IP development and testing process.

Key Skills:
Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer
Knowledge in ASIC/FPGA/SoC verification or development cycle
Knowledge in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
Strong communication, analytical and documentation skills and ability to interface with other groups/site
Programming skills (e.g.: C/C++, Perl, TCL or Python)