DFx/Diagnosis Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Lattice Semiconductor is seeking a Senior DFx/Diagnosis Engineer to join the Manufacturing team focused on DFx Design. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.

Accountabilities: 

• Define Scan methodology, architecture, and implementation strategies for FPGA SoC

• Perform top/block-level, ATPG generation and pattern simulation.

• Work with cross functional teams to ensure we are making the right trade-offs

• Verify DFT circuitry and interface with other blocks, debug timing simulation issues

• Drive backend ATPG initiatives to enhance front-end results while collaborating with front-end teams to ensure product success and maximize yield.

• Enhance and refine ATPG processes using industry-standard tools while applying new optimization techniques for FPGA.

• Shape front-end ATPG processes to improve test cost efficiency and coverage.

• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Required Skills

• Vast experience in DFT architecture and methodology.

• Knowledge of test models; test and pattern generation and verification; fault simulation, analysis and diagnostics

• Solid experience with DFT scan insertion and ATPG generation and verification.

• Vast experience to various EDA tools from Tessent, Synopsys and Cadence.

• Participated in at least one design from DFT specification to final pattern delivery for sub-system and/or SOC

• Experience in Silicon debug and bring-up of ATPG patterns on the ATE with an understanding of pattern formats, failure processing, and test program development

• Experience in FPGA DFT methodology is a plus with regards to fabric test techniques.