The role will also have significant responsibility in enabling next‑generation FPGA architectures, ensuring synthesis solutions scale effectively and remain competitive as Lattice platforms evolve.
Key Responsibilities
- Provide technical leadership in the design, implementation, and optimization of FPGA synthesis engines across multiple Lattice FPGA product families
- Collaborate closely with other synthesis developers to define architecture, algorithms, and long‑term technical direction
- Drive quality‑of‑results (QoR) improvements, including performance, area, and compile time
- Lead the development and enablement of new synthesis features and capabilities
- Maintain, enhance, and modernize existing synthesis software to ensure robustness, scalability, and long‑term maintainability
- Act as a technical escalation point for complex synthesis issues, including customer‑reported problems
- Influence engineering best practices, code quality, and design standards within the synthesis team
Technical Expertise
- Expert‑level proficiency in C++, with extensive experience designing, implementing, and optimizing large‑scale, performance‑critical software systems
- Experience leveraging GenAI‑based tools to improve developer productivity, accelerate debugging, enhance code quality, or support algorithm exploration and optimization
- Ability to apply modern software engineering practices while working in a highly optimized, systems‑level codebase
