Lattice Semiconductor is seeking a Design Verification Engineer to join the RnD organization.This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.
Responsibilities & Skills:
We are seeking a IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM/OVM.
Develop and Review Test Plan based on design specification
Develop constrained-Random verification environment for complex DUT
Implement coverage metrics using cover point and assertion
Create and debug tests for DUT
Resolve bugs with remote designers
Requirements:
Strong understanding of verification process from test plan to coverage completion
Strong communication and Analytical skills
Understanding of HDL (Verilog, SystemVerilog)
Experience with designing with FPGA is a plus
Programming skills (e.g.: C/C++, Perl, TCL or Python).
Experience in following technology areas are an added advantage : High speed SERDES protocols (PCIe, Ethernet, CPRI or JESD204B/C, USB), Memory (DRAM, SRAM, Flash, DMA), Interconnect (AMBA AXI, AHB, APB), Peripherals (SPI, I2C or I3C)
Education and General:
BS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of SystemVerilog/UVM
Independent and self-motivated, capable of executing under dynamic environment and uncertainties
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