A successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will lead research, design and development of FPGA primitives, Foundation IP, IP Catalog tooling as well as helping to refine Product Life Cycle e.g. planning, development & testing processes. The candidate is expected to play a lead role in cross-functional teams to plan and coordinate Lattice FPGA software release cycle including requirement analysis, feature scoping, development, testing and validation.
Requirements & Skills
Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields with 12+ years of experience in EDA SW Tool development .
Experience
Strong communication skills.
Knowledge or experience in FPGA architecture and FPGA software tools, specifically for device modeling and soft IP development.
Programming skills (C++ and Python).
Hands-on experience in FPGA RTL design, testbench development, logic verification, timing closure and debugging.
Preferred
Expert in multi-domain FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features.
Behaviors/Motivations
Technical leadership: Serves as a recognized technical authority who shapes Foundation IP technical roadmap across cross organization engineering decisions/efforts.
Accountability: Owns outcomes spanning multiple projects or releases, accountable for delivery, quality and sustainability while making explicit trade-offs to protect long term technical health.
Execution: Proactively identifies organizational and technical risks early, drives cross-team alignment, and leads resolution of complex execution challenges that span teams or functions.
Mentorship: Creates organizational leverage by mentoring engineers, developing technical leaders, setting technical direction, and establishing best practices adopted broadly and sustained over time.
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