Intern

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

We are seeking a Design Verification (DV) Intern who is passionate about shaping their career path in the FPGA design and verification industry.
•    Collaborate with design team to understand design implementation and define verification requirement.
•    Work with senior DV engineers on functional verification tasks, including test planning, test creation, and coverage closure.
•    Implement functional coverage, assertion, tests and sequence libraries following UVM methodology.

 

Requirements:
•    Good understanding of verification process from test planning to coverage completion.
•    Strong communication and analytical skills.
•    Basic understanding of HDL (Verilog, SystemVerilog).
•    Proficient programming skills (e.g.: C/C++, Perl, TCL or Python).
•    Familiarity with FPGA is a plus.

 

Education and General:
•    Currently pursuing Electronic or Electrical Enginnering or related engineering field.
•    Independent and self-motivated, capable of executing under dynamic environment and uncertainties