SystemC Simulation Model Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities:

• Create and maintain accurate SystemC models for security solutions.
• Implement Transaction-Level Modeling (TLM) interfaces for communication between models and other simulation environments.
• Validate SystemC models against hardware designs.
• Debug and resolve issues to improve model performance and stability.
• Work closely with architecture, design, and verification teams to define modeling requirements.

Required Skills, Experience

• BS/MS/PhD in Electronics or Computer Engineering with minimum of 6 years’ experience.
• Strong proficiency in SystemC and C++ (object-oriented design principles).
• Experience with TLM and hardware/software co-design methodologies.
• Familiarity with hardware description languages (VHDL/Verilog) is a plus.
• Knowledge of embedded systems architecture (processor architectures, memory hierarchies, bus protocols).
• Experience with using simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Graphics QuestaSim).
• Knowledge in using cryptography libraries is a plus.