Integration Design Engineer - Power Model

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Detailed Description

• Collaborate with all IP designers to ensure that tasks required for generating power numbers and developing power models are properly planned which include custom layout IP and ASIC IP

• Develop power models that cover multiple IPs and operating modes; this requires familiarity with schematic design, SPICE simulation, reading Liberty files, and analyzing power reports

• Understand IP functionality to define power estimation methodologies (vector-based or vector less) according to software requirements

• Utilize FPGA tools for power model calculations and apply them to derive subsystem or IP-level power models.

• Perform quality checks on power models from different IPs and consolidate them for software consumption, power calculator and estimation

• Correlate simulation-based power models with silicon data to enhance power estimation accuracy and improve customer experience

• Experience with FPGA power modeling and FPGA tool usage for power estimation is a strong advantage

• Working knowledge of PTPX, Totem, Voltus will be added advantage

Additional Job Description

• 10 years experience of hardware integration design

• Successfully went through whole development from start to Tape Out and correlate Silicon data with simulation data

• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation

• Familiar with floor-planning, power estimate, timing and back-end methodologies

• Experience with Linux scripting and Python

• Strong written and oral communication skills

• The ability to stay up-to-date with the latest advancements in technology and design

• Ability to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns