Silicon Integration Design Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Detailed Description

 

• SOC Integration Design Engineer, focus on power model generation which include flow & methodology.
• Work includes collaboration with architecture, verification and software teams to generate realistic power number for FPGA product.
• Work with all the IP designer to ensure all the work require to generate power number is plan and power model is deliver.  
• Power model will need to cover different IP different mode thus need to familiar with schematic design and spice simulation and able to read liberty file and analyze power reports.
• Understand IP functionality to strategy power number methodology vector/vectorless per SW requirement.
• Understand FPGA tools power model calculation and it usage to further derive to sub-system OR IP level power model work development.
• Quality check the power model from different IP and consolidate all power model for SW consumption.
• Correlate the simulation power model with Silicon data to improve power estimator customer experience.
• Experience with FPGA power model and FPGA tools usage of power number will be an added advantage.

 

 

Required Skills, Experience, Licenses:

• Successfully went thru whole development from start to Tape Out.
• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
• Experience power number generation for ASIC IP as well as custom layout IP.
• Familiar with floor-planning, power estimate, timing and back-end methodologies.
• Experience with Linux scripting in at least one of shell, and Python.
• Strong written and oral communication skills.
• The ability to stay up-to-date with the latest advancements in technology and design.