Key Qualifications
15+ years of dedicated/hands-on FPGA/SOC ASIC experience (Design, Verification and Validation)
At least 10 years’ experience in leading Subsystems/IPs team to deliver complex FPGA/ASIC Subsystem
Experienced in managing team to deliver FPGA IP and Subsystem for FPGA products
Experience in delivering Subsystems like Sensor Interface (MIPI DPHY, SLVS-EC), DSP IP (FFT, FIR) or Image Processing IP (Debayer, AWB, Gamma Correction etc).
Experience Interconnect Bus Fabric, AHB, AXI, based bus architecture
Should be a great team leader with excellent communication and problem-solving skills and the desire to seek diverse challenges.
Build a high performing team and retain talents
Education and General:
BS/MS/PhD in Electronics or Computer Engineering minimum of 15 years of FPGA IP and system design experience.
Independent and self-motivated, capable of executing under dynamic environment and uncertainties.
Innovative, problem solver who likes to come up with newer and better solutions for existing problems
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