Key Qualifications
- Over 20 years of comprehensive, hands-on experience in FPGA and SoC ASIC development, encompassing design, verification, and validation.
- More than 12 years of leadership experience managing teams responsible for delivering complex FPGA/ASIC subsystems and IP blocks.
- Proven expertise across the full ASIC lifecycle—from concept and architecture through design, verification, tape-out, and silicon bring-up.
- Extensive experience leading teams to develop and deliver high-speed interface subsystems and IP for FPGA and ASIC products.
- Proven experience in delivering high-performance subsystems, including PCIe (Gen3/4/5), Ethernet (10G–100G), LPDDR/DDR (4/5), USB (3.x/4.x), and MIPI C/D-PHY interfaces.
- Strong expertise in bus fabric design and integration, including AHB and AXI-based architecture.
- Demonstrated expertise in low-power design methodologies, system boot-up and power-cycling, device driver development, and hardware/firmware interaction, including design, verification, and validation.
- Exhibit strong leadership with exceptional communication and problem-solving skills, coupled with a proactive approach to embracing diverse and complex challenges.
- Build and nurture a high-performing team by attracting, developing, and retaining top talent. Establish clear career growth paths and leadership opportunities for technical experts within the team.
- Shape the future roadmap for high-speed protocols and establish a strategic charter that positions Lattice as a leader in delivering best-in-class devices.
Education & General Requirements
- BS/MS/PhD in Electronics or Computer Engineering, with a minimum of 20 years of experience in high-speed IP and system design.
- Self-motivated and independent, capable of executing effectively in dynamic environments with evolving priorities.
- Innovative problem solver, passionate about developing creative and optimized solutions to complex technical challenges.