Director, IP Design Engineering

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

We are seeking a Director of Design Engineering with strong cross-functional and technical leadership skills to define, plan, and drive the vision for high-speed IP and subsystem design portfolios at Lattice Semiconductor.

Responsibilities: 

• Define, plan, and execute the technical vision and development strategy for high-speed IP and subsystem designs, ensuring alignment with Lattice’s product roadmap and market needs.
• Lead and manage a high-performance engineering team in the end-to-end development of complex FPGA subsystems and IP cores, from architecture and design through verification, tape-out, and silicon bring-up.
• Drive the development and delivery of high-speed interface IP, including PCIe, Ethernet, LPDDR/DDR, USB, and MIPI, while ensuring performance, power, and area targets are met.
• Collaborate cross-functionally with software, validation, product, and marketing teams to ensure successful product definition, development, and deployment.
• Build and nurture a high-performing team by attracting, developing, and retaining top talent. Establish clear career growth paths and leadership opportunities for technical experts within the team.
• Shape the future roadmap for high-speed protocols and establish a strategic charter that positions Lattice as a leader in delivering best-in-class devices.

Key Qualifications：

• Over 20 years of comprehensive, hands-on experience in FPGA and SoC ASIC development, encompassing design, verification, and validation.
• More than 12 years of leadership experience managing teams responsible for delivering complex FPGA/ASIC subsystems and IP blocks.
• Proven expertise across the full ASIC lifecycle—from concept and architecture through design, verification, tape-out, and silicon bring-up.
• Extensive experience leading teams to develop and deliver high-speed interface subsystems and IP for FPGA and ASIC products.
• Proven experience in delivering high-performance subsystems, including PCIe (Gen3/4/5), Ethernet (10G–100G), LPDDR/DDR (4/5), USB (3.x/4.x), and MIPI C/D-PHY interfaces.
• Strong expertise in bus fabric design and integration, including AHB and AXI-based architecture.
• Demonstrated expertise in low-power design methodologies, system boot-up and power-cycling, device driver development, and hardware/firmware interaction, including design, verification, and validation.
• Exhibit strong leadership with exceptional communication and problem-solving skills, coupled with a proactive approach to embracing diverse and complex challenges.

Education & General Requirements：

• BS/MS/PhD in Electronics or Computer Engineering, with a minimum of 20 years of experience in high-speed IP and system design.
• Self-motivated and independent, capable of executing effectively in dynamic environments with evolving priorities.
• Innovative problem solver, passionate about developing creative and optimized solutions to complex technical challenges.