Staff FPGA Soft IP Design Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

We are seeking a highly skilled and motivated Staff FPGA Soft IP RTL Design Engineer to join our design team. In this role, you will be responsible for the design, development, and verification of high-performance Ethernet IP cores targeting FPGA platforms. You will work closely with system architects, verification engineers, and software teams to deliver robust and efficient Ethernet solutions.

Requirements

Key Skills

• Strong Proficiency in Verilog/SystemVerilog RTL design coding.

• Experience with FPGA toolchains (Vivado, Quartus, Synplify, etc.).

• Familiarity with simulation and verification tools (ModelSim, Questa, UVM, etc.).

• Solid understanding of timing closure, clock domain crossing, and FPGA constraints.

• Programming skills (e.g.: C/C++, Perl, TCL or Python) for Automated system level validation.

• Strong background or experience of Ethernet protocols (10/100/1G/10G/25G/100G), MAC/PCS layers, PTP1588, Auto Negotiation, Link Training and IEEE standards (e.g., 802.3) is a major plus

• Collaborate with verification teams to define test plans and support functional verification.

• Perform synthesis, timing analysis, and FPGA implementation.

• Support bring-up, debugging, and validation on hardware platforms.

• Work with software and firmware teams to ensure seamless integration.

• Maintain and improve existing IPs for performance, area, and power optimization.

• Document design specifications, user guides, and test procedures.

• Experience in serDes related HW validation equipment on FPGA platforms is a plus.

Education and General:

• BS/MS/PhD in Electronics or Computer Engineering minimum of 7-10 years of FPGA/RTL design experience.

• Strong written and verbal communication skills to work with cross-functional team

• Self-motivated and proactive with critical thinking.

• Good problem solving and de-bugging skills

• Experience and ability to lead a team of juniors is a plus