We are looking for a Senior QA Engineer to join our team with a specialized focus on Radiant QoR (Quality of Results). This role is critical in ensuring our FPGA design tools deliver optimal performance, area, power, and timing results. You will work closely with R&D, software engineering, and customer-facing teams to validate and enhance QoR across a wide range of real-world and synthetic designs.
Key Responsibilities
Design, develop, and execute comprehensive test plans and test cases for Radiant QoR flows.
Analyze synthesis, place-and-route, and timing results to identify regressions and drive improvements.
Acquire and integrate IP blocks, solution designs, and customer designs into the QoR validation suite to ensure real-world relevance and robustness.
Convert and validate designs across different Radiant device families, ensuring consistent QoR and functional correctness.
Automate QoR validation workflows using scripting languages (e.g., Python, Tcl, Shell).
Collaborate with development teams to triage issues, reproduce bugs, and verify fixes.
Maintain and expand regression test suites and dashboards to monitor QoR trends.
Provide detailed reports and insights on QoR metrics to stakeholders.
Mentor junior QA engineers and contribute to best practices in QoR validation.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in QA or EDA tool development, with a strong focus on FPGA or ASIC design flows.
Deep understanding of digital design, RTL (Verilog/VHDL), synthesis, and timing analysis.
Hands-on experience with Radiant or similar FPGA design tools (e.g., Vivado, Quartus, Libero).
Experience working with IP cores, reference designs, and customer design flows.
Proficiency in scripting languages such as Python, Perl, Tcl, or Shell.
Strong analytical and debugging skills, especially in interpreting QoR metrics.
Familiarity with CI/CD tools and automated testing frameworks.
Preferred Qualifications
Experience with Lattice Radiant toolchain and Lattice FPGA architectures.
Knowledge of low-power design techniques and timing closure methodologies.
Experience with design migration across FPGA families.
Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., Jira).
Experience working in Agile/Scrum environments.
Software Powered by iCIMS
www.icims.com