Job Description
A successful candidate will join a team designing and developing Lattice FPGA software tools in San Jose. The candidate will contribute to research, design and development of the software FPGA device model and configuration bitstream generation tools. The candidate is expected to work closely with cross-functional teams to plan and execute Lattice FPGA software release cycle including requirement analysis, feature scoping, development, testing and validation. The candidate also will be responsible for maintaining existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality.
Responsibilities & Skills
Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields with 5+ years of experience in EDA SW Tool development
Experience
- Strong communication skills
- Knowledge or experience in FPGA architecture and FPGA software tools, specifically for device modeling and/or bitstream generation
- Programming skills (C++ and Python)
- Hands-on experience in FPGA RTL design, testbench development, logic verification, timing closure and debugging including board validation
Preferred
- Working knowledge of protocols such as Serdes interface, Ethernet, PCIe or Memory DDR
Behaviors/Motivations
- Team Player: Works well as a member of a group
- Dedicated: Devoted to a task or purpose with loyalty or integrity
- Self-Starter: Inspired to perform without outside help
- Ability to Make an Impact: Inspired to perform well by the ability to contribute to the success of a project or the organization
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