Design Eng 2

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

We are looking for passionate digital design engineer to build High Speed Serial Protocol Hard-IP portfolio for Lattice FPGA. The individual should have the ability to work closely with Principal Engineer or Architect to translate specification into RTL design, for the best performance, low power and optimum logic utilization.

Accountabilities/Exposure:

• Own unit level design and IP integration.

• Own design quality check with exposure to various industry standard EDA tool and methodology.

• Design timing constraints definition and timing convergence.

• Design openbox test planning, assertion check coding and debug.

• Design code coverage analysis and closure.

• Support silicon power-on and post silicon validation

• New design methodology development.

• Scripting in flow automation on daily design execution tasks.

• Design documentation e.g. micro-architecture and design implementation document.

Qualification:

• Good understanding in ASIC/FPGA IP or SoC development cycle.

• Knowledge and experience in High-Speed Serial Protocols e.g.: Ethernet, PCIe, MIPI or Universal Transceiver.

• Proficient in RTL design with Verilog or System Verilog and design constraints.

• Experience in design quality checks methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.

• Advance user of logic simulation EDA tools e.g.: Cadence Xcelium, Synopsys VCS or Siemens Questa.

• Experience in working closely with Design Verification team on testplan, assertions coding, functional and code coverage analysis, tests debug.

• Familiarity or experience in Physical Design e.g.: Synthesis, LEC or Timing Closure.

• Programming skills (e.g.: Perl, Shell Scripting, TCL, Java, Python or C/C++) and familiar with Linux OS.

• Experience in technical writing e.g.: design micro-architecture documentation, paper publication or patent writing.

• Self-motivated, strong communication skills, promote innovation and teamwork.

• Experience in silicon power-on or hardware validation is a plus.