Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Create high-quality analog, mixed-signal and custom digital layout. At least 2+ years of proven in-depth experience in custom and semi-custom layout of various IPs including memory and array cells, analog and mixed-signal blocks, Serdes, and up to chip level layout integration.
The role includes IP block ownership, sector and full chip task support, chip-level layout integration support, methodology improvement participation, and schedule definition to implement assigned layout tasks. Duties include but not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), physical verification of cells up to chip-level (e.g. DRC, LVS, ESD, DFM, Antenna, EMIR, PERC, etc.), meet or beat task schedule, prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administrative tasks (e.g. task schedule definition). Run and analyze parasitic extractions.
Accountabilities:
Execute floor plan, routing and physical verification of custom IPs (analog, mixed-signal and custom digital). Create IP layout documentations and provide support until sign-off.
Provide support to sector and full chip activities such as physical integration and physical verification.
Work effectively with circuit designers to understand key layout constraints.
Proactively collaborate with EDA CAD group as issues arise.
Hold layout quality reviews of completed cells, macros and chip-level layout.
Recognize layout considerations pertaining to device matching, noise, shielding, and latch-up in analog, mixed signal and digital circuit.
Run and analyze parasitic extractions.
Required Skills
At least 2 yrs of solid Custom Layout Engineering industry experience.
Custom layout of IP blocks to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EM-IR, PERC, etc) using Siemens Calibre.
Experience in running, analyzing and debugging EM-IR using Cadence Voltus.
Experience in generating LPE is preferred.
Automation skill is a plus (e.g. Cadence SKILL scripting).
FinFET technology node experience is a plus.
PNR experience is a plus.
Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
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