Dfx/Diagnosis Principal Engineer

Job Title:

DFx/Diagnosis Principal Engineer

Job ID: 2025-3108

Location:

Hillsboro, Oregon

Position Duties:

Work as an integral part of the Global Operations and Quality (GOQ) group responsible for building High Coverage, diagnosable FPGA test patterns for Embedded IP in FPGA. Responsible from design phase of DFT until release of ATPG vectors and FPGA pattern generation to production. Establishing DFT methodology and verifying DFT solutions in complex SOC. Implement RTL code in FPGA and resolve any sensitivity issues during silicon bring-up.

Primary Responsibilities include:
•          Review DFx features to ensure high Stuck-At & Transition ATPG coverage
•          Review DFx features to ensure a final FPGA implementable, robust & diagnosable manufacturing pattern
•          Work with Verification / Design teams to own the Pre-Tapeout DFx verification of the embedded IP
•          Use Lattice FPGA software tools to build a FPGA design to accept ATPG vectors for multi-instance embedded IPs
•          Verify the design on silicon. Ensure FPGA pattern robustness across Voltage & Temperature in volume production

Position is eligible for part-time work-from-home.

Minimum Requirements:

Bachelor in Electrical Engineering or related field

7 years of experience as Electrical Engineer or related field

Prior experience to include:
• SOC DFT (SCAN / ATPG) methodology and DFT verification
• Developing robust FPGA patterns with demonstrated results on Silicon
• SOC design flow, verification and RTL coding for FPGA
• Debugging and Diagnosing FPGA patterns
• Script using Perl or Python and TCL coding
• Diagnosis methods to electrically isolate