Lattice Semiconductor is seeking a Design Verification Engineer to join the RnD organization. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.
As a Verification Eng., you will work with IP architect to understand IP features, create testbench architecture plan, work with IP designers to develop testplan, perform detailed testing of IP features and ensure coverage is met. You will need to ensure the IP is compatible with industry standard synthesis & simulator tools. You will also co-ordinate with IP designer on IP release mechanism for testing. You are also expected to develop scripts in Python and other script languages to automate the soft IP development and testing process.
Key Skills
Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
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