Job Summary:
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Create high-quality analog, mixed-signal and custom digital layout. At least 5+ years of proven in-depth experience on custom and semi-custom layout of various IPs including memory and array cells, analog and mixed-signal blocks, Serdes, and up to chip level layout integration. The role includes IP layout ownership, sector and FC physical integration support, and methodology improvement participation. Duties include but not limited to custom layout implementation of ECO (Engineering Change Order) and LCO (Layout Change Order), cells/IP/chip-level physical verification run (e.g. DRC, LVS, ESD, DFM, Ant, PERC, EMIR, etc.), prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administration of tasks (e.g. task schedule definition).
Accountabilities:
Full ownership of IP layout including resource projection, schedule management and sign-off documentation for Final Design Review. Sector custom routing ownership, full chip layout integration and physical verification support.
Work effectively with circuit designers to understand and implement key layout constraints.
Proactively collaborate with EDA group as issues related to CAD tools and flows arise.
Hold layout quality reviews of completed cells, IP block, sector and FC physical integration.
Recognize layout considerations pertaining to device matching, noise, shielding, ESD and latch-up in analog, mixed signal and digital circuit.
Run and analyze LPE, pre/post-layout simulations.
Required Skills
At least 5 yrs of solid Custom Layout Engineering industry experience.
Custom layout of IP blocks up to full chip layout integration using Cadence Virtuoso and full physical verifications (DRC, LVS, ESD, Antenna, DFM, PERC, etc) using Siemens Calibre.
Experience in running, analyzing and debugging EM-IR using Cadence Voltus.
Experience in generating LPE.
Automation skill is a plus (e.g. Cadence SKILL scripting).
FinFET technology node experience is a plus.
PNR experience is a plus.
Ability to manage performance of project team members.
Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
Lattice
Feel the energy.
Software Powered by iCIMS
www.icims.com