We are seeking an IP Validation engineering lead with significant hands-on experience in FPGA IP protocol validation, protocol compliance, FPGA hardware bring-up and debug.
Requirements
Key Skills
Hands-on experience in FPGA IP validation with protocol validation equipment is required
Experience with detailed IP validation plan creation and execution for IP and Subsystem design validation activities
FPGA-based RTL design flows , which include FPGA design entry with Verilog, Timing Closure, Board Bring-up and Debug with analyzers/scopes
Programming skills (e.g.: C/C++, Perl, TCL or Python) for Automated system level validation
Strong background and Experience in either Serdes or memory protocols (e.g.: PCIe, Ethernet, DDR) and familiarity on associated validation equipment
Experience on board development is a plus
Experience with standard bus protocols like AMBA AXI, and APB, JTAG, UART, I2C/I3C
Experience in leading a team on hardware-based validation is a plus
Education and General:
BS/MS/PhD in Electronics or Computer Engineering minimum of 8 - 12 years of FPGA or semiconductor Post-Silicon validation experience
Strong written and verbal communication skills to work with cross-functional team
Self-motivated and proactive with critical thinking
Strong problem solving and de-bugging skills
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