Integration Team Lead

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Detailed Description

• Hardware Integration Design Lead is responsible driving, by example, the team of engineers to perform FPGA related integration tasks.

• Performs the implementation of either sections or full chip, by understanding requirement of individual IPs, how they work together at system level and then SOC them all together.

• Work includes collaboration with architecture, verification and software teams.

• Responsibilities include scripting, rtl or schematic design, power and size estimates, generation of the address maps, working with packaging on pin migration, design checks and timing analysis.

• Help with chip bring-up, validation, and characterization.

Required Skills, Experience, Licenses:

• 5-10yrs experience of hardware integration design

• Have been lead or manager to the group of 3 to 10 engineers

• Successfully went thru whole development from start to Tape Out of at least 2 products.

• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.

• Working knowledge of System Verilog, synthesis, and static timing analysis

• Good understanding of DFT methodology on IP and chip level

• Specialist in floor-planning, power estimate, timing and back-end methodologies

• Experience with Linux scripting in at least one of shell, and Python

• Experience and knowledge of PnR is a plus but not a must

• Strong written and oral communication skills

• The ability to stay up-to-date with the latest advancements in technology and design