Detailed Description
Hardware Integration Design Engineer is responsible for implementation of either sections or full chip, by understanding requirement of individual IPs, how they work together at system level and then SOC them all together.
Work includes collaboration with architecture, verification and software teams.
Responsibilities include scripting, rtl or schematic design, power and size estimates, generation of the address maps, working with packaging on pin migration, design checks and timing analysis.
Help with chip bring-up, validation, and characterization.
Required Skills, Experience, Licenses:
8 yrs experience of hardware integration design
Successfully went thru whole development from start to Tape Out of at least 2 products.
Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
Working knowledge of System Verilog, synthesis, and static timing analysis
Good understanding of DFT methodology on IP and chip level
Specialist in floor-planning, power estimate, timing and back-end methodologies
Experience with Linux scripting in at least one of shell, and Python
Experience and knowledge of PnR is a plus but not a must
Strong written and oral communication skills
The ability to stay up-to-date with the latest advancements in technology and design
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