CAD Eng 2

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Lattice is seeking a CAD/EDA Engineer that is experienced in VLSI design & EDA, to join our CAD/EDA Engineering group in Manila, Philippines. Qualified candidates must be either BS EE/ECE/COE, or MS graduate with 5 to 10 years of industry experience on 5/7/16/28 nm process technology nodes. This individual will be one of the key drivers to develop and support the logic/digital design methodology & flows.

Accountabilities:

The candidate's general responsibilities include the following:

• Develop and support RTL synthesis/DFT, PNR, STA design methodologies & flows automation

• Focus on physical design place and route and STA tape-out flows for advanced FINFET nodes (7nm or below)

• Experience in designing and tape-out any IP block or full chip integration for designs on 5/7/16/28nm process nodes

• Drive cross functions initiatives & design methodologies

• Create, release, and maintain design scripts to automate EDA tool flows in synthesis and physical design and QA area

• Tracking and resolution of tool and technology file issues with hands-on management by objectives of Foundry and EDA vendor support teams

• Define and implement comprehensive design QA procedures and test suites for backend PNR flow

• Document and delivery training on developed methodology and EDA flow

• Monitor EDA industry trends and new capabilities by attending conferences and research forums

Requirements:

• BSEE/CE, or MSEE with at least 6 years of industry EDA experience on advanced FINFET nodes

• Knowledge of Verilog and System Verilog

• Good knowledge in timing analysis (AOCV)

• Tool ECO flow post-CTS/post-route

• Clock tree synthesis (Experience in zero skew CTS - Clock Mesh)

• Mixed signal (plus with Cadence MSOA flow)

• Experience in high-speed design (PNR requirement)

• Early IR analysis (Power analysis)

• Expert in physical design flows using Cadence/Synopsys PNR tools. Knowledge of DRC/LVS/ERC verification, LPE, and SPICE simulation are strong plus!

• Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation

• Expert in Unix Shell, utilities and scripting language such as Perl/TCL/Python • Excellent interpersonal, communication, and presentation skills, along with strong multitasking skills, attention to details, and ability to work well in a team & time zone • Knowledge of webpage design such as wiki/SharePoint

• Good organization skills