Staff Design Verification Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Inviting candidates with a passion for invention and self-challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s Silicon Engineering team has embarked upon to date. As part of our team, you will have the opportunity to take the lead on and contribute to verifying complex FPGAs.

This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world!

You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Serial protocols, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc.

You'll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs. This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art methodologies.

Description

Understand details of various protocol technologies, such as DDR SDRAM Memory, AMBA based On-Chip Interconnect, Ethernet, Video (DisplayPort, MIPI, HDMI, SDI), JESD204B, PCIe. This includes understanding the implementation of these technologies in Lattice IP’s. Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. Create IP level module and sub-system verification plan, TB, portable test benches, sequences, test infrastructure. Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level, achieve targeted coverage, work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall FPGA design.

Key Qualifications

• BS or MS Electrical/Computer Engineering, Computer Science, or related field of study

• 8+ years of dedicated/hands-on FPGA/SOC ASIC DV experience

• At least 5 years’ experience in leading a DV team to verify complex FPGA/ASIC

• Proven track record of working full ASIC verification from concept to tape-out to silicon bring-up.

• Advanced knowledge of System Verilog and UVM methodology

• Experience in using programming languages such as C/C++, Perl/Python/Tcl for automation of DV tasks

• Experience in verifying Subsystems like DDR SDRAM Memory, AMBA based On-Chip Interconnect, Ethernet, Video (DisplayPort, MIPI, HDMI, SDI), JESD204B, PCIe.

• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.

• Experience in hardware validation and debug is a plus