IC Layout Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Create high-quality analog, mixed-signal and custom digital layout. At least 2+ years of proven in-depth experience on custom and semi-custom layout of various IPs including memory and array cells, analog and mixed-signal blocks, Serdes, and up to chip level layout integration.

The role includes IP block support and/or ownership, full chip task support, chip-level layout integration support, methodology improvement participation, and schedule definition to implement assigned layout tasks. Duties include but not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), physical verification of cells up to chip-level (e.g. DRC, LVS, ESD, DFM, Antenna, EMIR, PERC, etc.), meet or beat task schedule, prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administrative tasks (e.g. task schedule definition). Run and analyze parasitic extractions.

 

Accountabilities: 

• Execute floor plan, routing and physical verification of custom IPs (analog, mixed-signal and custom digital). Create IP layout documentations and provide support until sign-off.

• Provide support to full chip activities such as physical integration and physical verification.

• Work effectively with circuit designers to understand key layout constraints.

• Proactively collaborate with CAD group as issues arise.

• Hold layout quality reviews of completed cells, macros and chip-level layout.

• Recognize layout considerations pertaining to device matching, noise, shielding, and latch-up in analog, mixed signal and digital circuit.

• Run and analyze parasitic extractions.

Required Skills:

• At least 2 yrs of solid Custom Layout Engineering industry experience.

• Custom layout of IP blocks to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, PERC, etc) using Calibre.

• Experience in generating LPE and simulations is preferred.

• Scripting skill (e.g. SKILL) is a plus.