Sr. FPGA IO Design Engineer

Lattice Semiconductor is seeking a Senior FPGA IO Designer to join the Engineering team will be responsible for researching, designing, developing, and testing Lattice’s current next generation IO designs. 

This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow. 

Accountabilities:  

• Development of FPGA-based General-Purpose IO IPs to enable IO solutions. Drive IO Architecture & uArchitecture studies with design trade-offs to align with Lattice Semiconductor product requirements. 

• Provide technical guidance and mentorship to the FPGA design team. 

• Good understanding of technical industry IO standards & specifications. Deep knowledge of memory protocols (DDR4, DDR5, LPDDR4, LPDDR5), differential protocols (MIPI D-PHY, C-PHY) and standard JEDEC protocols servicing high voltage (LVDS, RGMII, MDIO, SPI, etc…) 

• Experience driving various memory system topologies. 

• Experience in working with back-end and layout engineers on macro & chip-level floor-planning, power bus planning, etc.  

• Write / Maintain Design Documentation / Specifications. 

• Maintain up-to-date records of design changes and improvements. 

• Conduct design reviews and provide feedback to ensure high-quality deliverables.  

• Ensure the implementation of best practices in FPGA design and verification. 

• Oversee definition, design, verification, and documentation for General Purpose IO Designs.  

• Automate design tasks to complete the design in the most efficient approach. Champion productivity improvement metrics within the hardware organization.  

• Drive Signal integrity Analysis.  

• Work closely with peers in layout, structured design, validation, emulation, verification, layout, architecture, FPGA software and product characterization groups. 

• Manage project timelines, deliverables, and resources.

• Coordinate with cross-functional teams to ensure project milestones are met. 

• Experience with post-silicon bring up debug. Prior experience driving root-cause of complex silicon issues. 

• Experience setting timing & power targets for custom analog and digital IPs and driving timing power rollup and correlation activities. 

• Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.  

• Experience with strong leadership skills and the ability to mentor designers. Excellent interpersonal skills, including written and verbal communication.

Required Skills:

• MS or PhD in Electrical Engineering or equivalent with 10+ years of experience.  
• Knowledge and experience of IO design for low & high speed interfaces.       

• Experience with memory system design DDR4/5, LPDDR4/5 from product definition to productization. 

• Experience with MIPI D-PHY, C-PHY from architecture to productization. 

• Knowledge of signal integrity and timing analysis for high-speed IO designs. 

• FPGA architecture knowledge a plus.                         

• Ability to manage multiple projects and prioritize tasks effectively.

• Experience with hardware debugging tools and techniques. 

• Must be detail oriented with strong customer service skills. 

• Able to demonstrate excellent analysis and problem-solving skill. 

• Demonstrated capacity to work with minimal direction.     

• Strong communication and leadership skills.