SW Test / QA 5

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

We are seeking a highly skilled and experienced Software QA Test Engineer to join our dynamic team. As a senior QA Test Engineer, you will play a pivotal role in ensuring the quality and reliability of our software tools and foundation IP. Your expertise will extend beyond standard testing practices, as you oversee critical aspects of the verification process and mentor junior engineers.

Responsibilities:

1. Comprehensive Verification: Validate FPGA design flows, including compilation, simulation, power analysis, timing, and bitstream generation. These flows are closely integrated with FPGA IP components.
2. Strategic Test Planning: Develop, maintain, and enhance test plans specifically tailored for FPGA IP blocks and software verification tools.
3. Precise Execution: Define and write detailed test cases for functional and performance verification of FPGA IP blocks.
4. User-Centric Validation: Ensure that the FPGA IP catalog offers an intuitive and error-free user interface.
5. Coverage Optimization: Analyze coverage metrics and refine test scenarios to achieve thorough coverage goals.
6. Collaboration and Requirements Analysis: Review, collaborate, and analyze feature requirements with stakeholders to align testing efforts with overall project goals.
7. Mentoring Junior Engineers: Coach and guide junior engineers, sharing best practices, providing technical support, and fostering their professional growth.

Education: 

Bachelor’s or Master’s degree in Electronic Engineering, Computer Science, Software Engineering, or related fields.

Experience:

1. A minimum of 18 years of experience in software/IP testing and quality assurance, with a proven track record in IP block verification.
2. Proficiency in Verilog, System Verilog, and VHDL. Knowledge of UVM is a plus.
3. Strong experience in Simulation/Verification using tools such as VCS, Questa, and power analysis within FPGA design flows.
4. Familiarity with FPGA architecture and silicon features (e.g., SERDES and DDR) is advantageous.
5. Exposure to GUI testing platforms like Squish is beneficial.

Soft Skills:

• Analytical and Problem-Solving Abilities: You excel at dissecting complex issues and finding effective solutions.
• Effective Communication: Your ability to collaborate and communicate with cross-functional teams is essential.
• Attention to Detail: You proactively identify quality issues and contribute to continuous improvement.
• Innovative Mindset: Your creativity drives improvements in testing methodologies and processes.

Competitive benefits package including:

• Medical (HMO), dental, vision effective on date of hire
• Employee Stock Purchase Plan, Well-being Programs, Tuition Reimbursement and more