P&R Distinguished Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Role specifics:

• This is a full-time individual contributor position located in Pune, Indea
• The role may either focus on FPGA projects concentrated in Pune; or as part of a broader physical design organization that contributes to efforts worldwide.
• The qualified candidate will be a world-class expert in physical designs (either Innovus or ICC2 flows)
• The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the particular complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.

Accountabilities:

• Serve as a key contributor to FPGA design efforts
• Drive physical design of ASIC flow blocks on the FPGA (e.g., DDR PHY, configuration and security engines, interface wrappers around serdes PMAs, etc.)
• Work closely with design team on static timing constraints, placement/routing pragmas and heuristics, clock synthesis, test insertion, timing closure, and ECO flows.
• Bring best-in-class methodologies to accelerate design time and improve design quality.
• Think creatively on using ASIC flow physical design in the construction of FPGA fabrics (traditionally highly custom design blocks)
• Develop strong relationships with worldwide teams.
• Mentor and develop strong partners and colleagues.
• Occasional travel as needed.

Qualifications:

• BS/MS/PhD Electrical Engineering, Computer Science, Computer systems degree or equivalent.
• 15+ years of experience in driving physical design across a multitude of silicon projects.
• Familiarity with FPGA designs, use-cases, and design considerations is a plus.
• Independent worker with demonstrated problem-solving abilities.
• Proven ability to work with multiple groups across different sites and timezones.