Verification Eng Intern

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Lattice is looking for a highly motivated verification engineer with relevant education background to be part of the verification team in Shanghai working on state-of-art chip product development.

Responsibilities:

• Work with other verification engineers on IP level and Sub-system verifications.
• Created UVM based test cases to meet coverage goals.
• Optimize scripts to improve team work efficiencies.

Requirements:

• MSc in EE or relevant subjects.
• Course work project experiences on Verilog, system Verilog is preferred.
• Can write and read in English for project work.