Staff Platform Validation Engineer

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.

The Company's broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.

Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice…and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what’s next.

We are seeking a Staff Platform Validation engineering lead with significant hands-on experience in FPGA hardware/development kit, FPGA timing closure and hardware bring-up/debug. The candidate is expected to lead a team of 5 engineers on Lattice Platform Validation.

Requirements

Key Skills

• Hands-on experience in FPGA hardware/development kit is required
• Experience with detailed test plan creation and execution for block-level and system-level designs
• FPGA-based RTL design flows and methodology to generate the bitstreams and debug using internal logic analyzer(Reveal or ILA etc)
• Programming skills (e.g.: C/C++, Perl, TCL or Python) for Automated system level validation
• Experience on board development is a plus
• Experience with standard bus protocols like AMBA AXI, and APB, JTAG, UART, I2C/I3C
• Experience in leading a team on hardware based validation is a plus
• Strong background and Experience in either Serdes or memory protocols (e.g.: PCIe, Ethernet, DDR) and familiarity on associated validation equipment

Education and General:

• BS/MS/PhD in Electronics or Computer Engineering minimum of 8-10 years of FPGA or semiconductor experience
• Strong written and verbal communication skills to work with cross-functional team
• Self-motivated and proactive with critical thinking
• Good problem solving and de-bugging skills

Competitive benefits package including:

• Medical (HMO), dental, vision effective on date of hire
• Well-being Programs, Tuition Reimbursement and more