Staff Verification Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Design Verification Engineer will be responsible for verifying all design views from behavioral hard IP up to Full chip SoC level. The engineer should be able to create testplan, design and architect testbench, do functional simulation, analyze and debug the design, communicate all findings to the design team and extract verification metrics to sign-off the design.

Job Detailed Description
• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
• Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
• Understand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment
• Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
• Define and design verification regression environment
• Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
• Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
• Develop best practices and world class methods for SoC verification

Qualifications:
• at least 8 years Digital Design Verification Related Experience
• Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer
• Skill in debugging and analyzing complex digital design
• Experience in Verilog Languages and Methodologies
• Knowledge in verification or development cycle
• Knowledge in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
• Hands-on experience in Python, Perl or Shell Scripting, TCL and Make.
• Strong communication, analytical and documentation skills and ability to interface with other groups/site
• Stay up to date on industry trends and direction of verification technology development

Competitive benefits package including:

• Medical (HMO), dental, vision effective on date of hire
• Employee Stock Purchase Plan, Well-being Programs, Tuition Reimbursement and more